Pcell (parametrized cell) implementation on layout in Cadence Virtuoso | pcell with Example | part-4

This cadence tutorial shows how to implement the pcell on a drawn layout in Cadence Virtuoso. What is pcell, how to use pcell, where to use pcell, how to draw the pcell, all are explained in this tutorial from scratch. Pcell implementation step by step with example in Cadence virtuoso has been explained here. Pcell stands for Parametrized cell, a technique to make a variation in different parameters of an existing layout. We draw a basic layout of the device and implement the pcell in its various parameters so that later we can use this layout to generate a variety of similar devices with different dimensions with help of pcell. Pcell saves lots of time in custom layout design. This is the 4th video in the layout series of the video session. In this series of Video tutorial first, we will draw the layout of some basic devices and then we will move to pcell implementation of customed layout devices. Next we will do layouts of some basic circuits followed by Design Rule Checks ( DRC ), Layout Vs Schematic Check (LVS), Parasitic Extraction (PEX) and finally post-layout simulation in cadence tool. Link of of all the videos of this session is here 1. Layout of nmos: https://youtu.be/Ksq1NlTmwKM 2. Layout of pMOS https://youtu.be/CMiI7e6Noso 3. Layout of BJT https://youtu.be/zFLmuZa4tDE 4.Pcell Implementation in Layout https://youtu.be/cl43omqKdKs 5. DRC check, Simulation and other explanations https://youtu.be/jbE8ejVHDIU 6. LVS, PEX and Post Layout Simulations https://youtu.be/rojcmjqExbE If you feel this video is relevant to your domain and useful, please like the video and subscribe to the channel and share with your connections. Your queries/suggestions are most welcome in the comment section. Please comment on your reaction. #Pcell #PcellInCadence #PcellWithExample