LVS (Layout vs Schematic)Check in Cadence | using Calibre | PEX | Post Layout Simulation in Virtuoso

This tutorial shows how to do Layout vs Schematic (LVS) checks in Cadence Virtuoso using Calibre tool of MentorGraphics. Solving of DRC violations, Parasitic Extraction (PEX) in Cadence using Calibre and Post Layout Simulation has also been demonstrated in this video. This is 6th session of this Layout series of Videos, In continuation with session-5, some DRC errors were introduced and shown how to remove those errors. Then Layout Vs Schematic (LVS) check has been done using Calibre. Now after the layout is DRC and LVS clean, we moved to Parasitic extraction (PEX) step using the Calibre tool. We extracted the parasitics associated with layout and visualized that. A post-layout simulation has been performed after the PEX and compared pre-layout and Post layout simulations output together. Links of all the videos in this series are as follows 1. Layout of nmos: https://youtu.be/Ksq1NlTmwKM 2. Layout of pMOS https://youtu.be/CMiI7e6Noso 3. Layout of BJT https://youtu.be/zFLmuZa4tDE 4.Pcell Implementation https://youtu.be/cl43omqKdKs 5. DRC check, Simulation and other explanations https://youtu.be/jbE8ejVHDIU 6. LVS, PEX and Post Layout Simulations https://youtu.be/rojcmjqExbE * Integration of Calibre tool in Cadence Virtuoso https://youtu.be/dtwVKUuH1Hs If you feel this video is relevant to your domain and useful, please like the video and subscribe to the channel and share with your connections. Your queries/suggestions are most welcome in the comment section. Please comment on your reaction. #LVS #PEX #PostLayoutSimulations