TRB Computer Science - Computer System Architecture - DMA - Direct Memory Access #4

TRB Computer Science - Computer System Architecture - DMA - Direct Memory Access Tamil Nadu TRB computer instructors Grade1 exam Video content in PDF available @ http://yaazhschool.in/computer_system_architecture/direct_memory_access.html ----- Direct Memory Access How data are copied to our Pen drive or other storage devices? How data transfer is working? Modes of Data Transfer 1. Programmed I/O o CPU runs a programme and transfer the data o CPU check the I/O device whenever it needed and transfer the data 2. Interrupt driven I/O o As soon as I/O device is ready, it will indicate the CPU to use it and transfer the data by CPU 3. DMA – Direct Memory Access • With Programmed I/O and Interrupt driven I/O, o CPU takes care of transfer o System performance get reduced o Probability of data loss is high due to the speed difference between CPU and I/O o It need at-least 2 clock cycles to complete the transfer • DMA is resolve the above problems • DMA is a process / an operation to transfer data from one resource to another resource without CPU • To copy data from HDD to pen drive, CPU is not necessary • CPU is general purpose processor and has lot of work has to be done by CPU in a computer system. • DMA is speed up the memory operations • DMA reduces the CPU interaction in data transfer, so CPU utilization will be high in the system How DMA works without CPU? DMAC – Direct Memory Access Controller • It’s a controller (a chip) specially designed for Data transfer • Invented by Intel • In DMA process, DMAC will take over the control of the Bus and become master of it until the transfer is completed or CPU revoke the grant of master of bus o I/O device request the DMAC (DRQ) to transfer data o DMAC request CPU to grant bus to use (HLQ – Hold request) o CPU grants the access to use bus by DMAC (HLDA – Hold Acknowledgement) o DMAC performs the transfer o DMAC acknowledge the CPU that transfer is complete o DMAC registers  Source Address  Destination Address  Word Count also called byte count  Control statement (Read / Write) Well, so far so good. But, CPU also has its own process and need Bus to use, in this case DMAC does not know when CPU will revoke the bus access and take over the bus control again. • So, DMAC has a buffer in it, to store some set of data • DMAC fist keep the data in Buffer from I/O and transfer data from Buffer to destination, it helps DMAC to avoid data lose. • Buffer could get filled even before DMAC gets access to bus from CPU, once get the access it starts transfer and so on When CPU grants access to bus by DMAC? • Instruction Cycle o Time execute to one instruction by CPU o DMA request come to CPU anytime during the Instruction cycle o Divided into multiple machine cycles / process cycle  Also can be divided into many states  Fetch OpCode  Decode OpCode  Fetch Operand  Execute Operation  Store Operand • Cycle Stealing o DMAC get bus access while CPU is busy and executing an Instruction, when CPU is not utilizing the BUS o It is another main advantage over Interrupt driven I/O (waits till Instruction completes) o Downside is, CPU may need extra clock cycle to take over the control of bus • x = a^2 * 5 + b + c o Fetch a – CPU need bus o SQRT a – CPU does not need bus o Multiply by 5 – CPU does not need bus o Fetch b – CPU need bus o Add the accumulation to b – CPU does not need bus o Fetch c – CPU need bus o Add the accumulation to c – CPU does not need bus o Store the value to x – CPU need bus o Next instruction cycle starts