S-10 | Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo

This is the session-10 of RTL-to-GDSII flow series of video tutorial. In this session, we will have hands on on the innovus tool for full PnR flow. We will start with gate level netlist and sdc file and do florplan, placement, CTS, routing and verifications of layout. Complete flow of innovus tool has been demonstrate in this video. Both command line and GUI mode has been covered in the same video. Important input files for this flow has also been discussed and how to create them has been explained. In this RTL-to-GDSII flow of video series, there are total 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow. 1. session-1 : Overview of RTL to GDII flow | Basic terms in the flow | EDA tools link: https://youtu.be/THXPuNNdPqw 2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files link: https://youtu.be/S4Yzexeq3l8 3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo link: https://youtu.be/RDtGyHfP_eQ 4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler Link: https://youtu.be/tLVAyfTfTNY 5. Session-5: Logic Synthesis | Design Compiler | Command line | gate level netlist Link: https://youtu.be/sIDe76QFG2g 6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision Link: https://youtu.be/N3CCQmcX3fk 7. Session-7: Logic Equivelence Check usign Formality |S8| RTL-to-GDSII flow | Formality tutorial Link: https://youtu.be/CFRqPnqifx0 8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow Link: https://youtu.be/1kLUdi0qNBo 9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial Link:https://youtu.be/OMhTtqnzDOA 10.Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial Link: https://youtu.be/TDvq1hVXzRc